FIG. 1 illustrates a carry look-ahead adder 100 to add two four bit values and a carry input. One four bit value is denominated A0, A1, A2 and A3, while a second four bit value is denominated B0, B1, B2 and B3. The carry input is denominated C0. Each input is gated through a flip-flop 102. The input values, say A3 and B3, are processed to form a generate bit G3 and a propagate bit P3. The generate bit is produced in accordance with a logical AND function at AND gate 104, while the propagate bit is produced in accordance with a logical OR function at OR gate 106. Accordingly, for the given possible inputs, the outputs of Table 1 are produced.
TABLE 1Generate Value fromPropagate Value fromInput AInput Blogical AND functionLogical OR function0000010110011111
The inputs are also applied to an eXclusive-OR gate (XOR) 108. That is, the inputs operate as a sum operand at the XOR gate 108. The other sum operand is from logical OR gate 110. Logical OR gate 110 receives an input from logical AND gate 112, which has a carry in input C0.
In FIG. 1, the gating flip-flops 102 are before the generate and propagate logic. If the flip-flops are positioned after the generate and propagate logic, a larger number of flip-flops is required, as shown in FIG. 2.
FIG. 2 illustrates a carry look-ahead adder 200 with flip-flops 202 positioned after the generate and propagate logic. Consequently, 17 flip-flops are required, as opposed to the configuration of FIG. 1, which requires 9 flip flip-flops at the input. This proliferation of flip-flops is attributable to the need to gate the input signals that operate as a sum operand for XOR gate 108.
This is a common problem when registers (e.g., flip-flops) are placed within a functional unit (e.g., a carry look-ahead adder). A functional unit commonly has a fan-out of logic, resulting in more signal lines within the functional unit than there are at the inputs and outputs of the functional unit. The additional registers increase power consumption, heat generation and the silicon footprint. It is desirable to minimize register use since registers require much more space than logical gates and consume more power, thereby producing more heat.
Registers provide an important timing or gating function and therefore the location where they are used is carefully chosen. Timing constraints sometimes require the utilization of registers within a functional unit. Consequently, it would be desirable to provide an architecture that allows for register placement within a functional unit, while maintaining the same number of registers utilized by register placement external to the functional unit.